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Azur Electronics


April 2017

The HP 3763A Error Detector on initial testing failed the Operator's Checks. The Adjustments including power rails are ok. Converted the front panel connections: Clock Input and Input A from 75Ω to 50Ω.  The Trigger Output is already 50Ω. Front panel connections: Clock Output; Count Gate Input; Sync Input are all ECL. Started working through the Troubleshooting procedures.

Local and Interval Times
Interval Time should start up as 00 00. Tricky fault turned out to be a failed buffer/driver output A14 IC5 holding the bus low.

Counter Gate Output on Rear Panel had no output. Fuse  A8 F2 replaced.

None of the odd numbered Word switches were working. Flip-Flop A7 IC9 had failed.

Testing A14 PCB
October 2019

More work completed on evaluating the HP 3762A Data Generator and HP 3763A Error Detector system. As well as the crystal controlled frequencies of f1 (139,264MHz) and f2 (68,736MHz) for 140Mbit/s and 68Mbit/s testing, by using an external clock input a wide bandwidth of 1kHz to 150MHz plus is available.
Rear Panel Connectors and Switches
Initial Power-Up Condition and f1 Frequency Offset
f2 Frequency Offset and Bit Error Rate 
Manual Count Start and Stop
The MEASUREMENT switch provides frequency offset, bit error rate and count options.

The 3763A appears to be working correctly, but has not been fully tested.

March 2021

The are some subtle and undocumented differences between the HP standard version and this BT special version of the 3763A. This has meant that the test procedure is different in some repects to the Service Manual. 
Now considered to be tested ok.